Developing verification methodologies as FPGAs take over from gate arrays

摘要

To maintain competitive, many designers have found that high level description languages (HDLs) are essential for describing and verifying their designs. ASIC designers adopted the HDL design and verification methodology several years ago because it works at a higher level of abstraction, eases the reuse burden, is portable between point tools, and generally allows designers to produce more gates per day. As FPGAs are now gate array replacements, this feature explores suitable verification strategies for the latter.