ISTFA 2011 User's Group 2 - '3-D Packaging and Failure Analysis'

摘要

With the need to increase performance and reduce power, 3-D packaging reveals new opportunities to provide high bandwidth and interconnect speed, achieve the highest capacity and volume ratio, as well as lower power consumption. The 3-D IC integration continues to increase in complexity, employing advanced technologies such as through-silicon via (TSV), wafer-to-wafer bonding, and multichip stacking. This drives more samples into failure analysis labs for development support, reliability studies, and failure analysis. It is very challenging for the existing defect localization and fault isolation methods.