Practical design for transferring signals between clock domains: a simple circuit addresses the errors and limitations of asynchronous design

摘要

With the increasing integration of multiple systems on single SOCs (systems on chip) or boards, multiple clock frequencies in single digital designs have become common. Because of the asynchronous nature of these designs, passing data or control signals between logic operating on different clock frequencies presents a special set of problems. Because asynchronous design is unfamiliar to most experienced digital designers, errors are common. Many of these errors find their way into the silicon and even into production because they are nearly impossible to detect in simulation and easily missed in postsilicon validation. Problems of performance degradation, back-end FDA-tool incompatibility, and dependency on the frequency relationship of the clocks involved often plague even functionally correct implementations. Frequency dependency is problematic for production tests that run the parts at different speeds, and it limits reusability in future designs with different system frequencies. You can address all of these errors and limitations with a fairly simple circuit that works for both data and control logic.