Optimised reversible divider circuit

摘要

Reversible logic has received a great deal of attention from many researchers over recent years for its enormous potential for application in quantum computing and nanotechnology due to its ability to reduce power consumption, which is the main requirement in low power VLSI design. In this study, first, we have presented new reversible blocks. These circuits can be used for the design of a large and complex combinational circuit. Then, we presented optimised designs for the various reversible components: multiplexers, registers, and shift registers. We will put forward the design and evaluation of optimised reversible division hardware to submit an application of reversible logic design. The comparative results show that the proposed designs individually have less hardware complexity, garbage outputs, constant inputs, quantum cost and significantly better scalability than the existing works. We have presented some lower bounds on the cost-metrics for designing the reversible components of the divider circuit.