A 6-GHZ ALL ALL-DIGITAL PLL FOR SPREAD SPECTRUM CLOCK GENERATORS (SSCG)

摘要

A 6-GHz all-digital phase-locked loop (PLL) has been fabricated in a 90-nm CMOS technology for SSC generation. The analysis and design of this 3rd order ADPLL is presented. A two-stage delta-sigma modulator is employed in this all digital PLL to improve the electromagnetic interference (EMI) reduction. The simulated EMI reduction is 19.8dB with 5000 ppm down spread to 5.97 GHz.