Voltage-Island based Floorplanning in VLSI for Area Minimization using Meta-heuristic Optimization Algorithm

摘要

Floor planning is the primary step of the physical design in the Very Large Scale Integration (VLSI) design flow. It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections. In the modern physical design of VLSI chips, it is essential to design the chip, which works with multi-supply voltages (MSV). To achieve power optimization, MSV circuits are partitioned into voltage islands (VI) where each island occupies an adjoining physical space and operates at one supply voltage. Since, floorplanning is a NP-hard problem, many optimization techniques were adopted in literature. In the proposed work, a new two step methodology is used for VI constrained fixed-outline nonslicing floorplanning based on meta-heuristic optimization algorithm, with the aim of reducing the total chip area. Here, a music-inspired Twin Memory Harmony Search (TMHS) is used as the meta-heuristic optimization algorithm. The experimental results show that our proposed approach provides efficient floorplanning with reduced area and wirelength. Experiments on MCNC benchmark circuits validate the effectiveness of our work.