FPGA Implementation of Image Compression and Denoisng Scheme for Satellite images

摘要

In this paper, the authors present high-speed pipeline architecture for lifting-based discrete wavelet transform (DWT) which is used for the image compression and FPGA based modified bilateral architecture is also proposed for denoising the satellite images. The proposed architecture is composed of pipeline rows, column processors and registers. Moreover, it is the combination of lifting DWT and modified bilateral filtering to perform the compression, denoising and reconstruction of image with N × N resolution. Complexity of the architecture is reduced by using shift-add logic. The proposed architecture is superior to the existed architectures in speed, hardware utilisation for similar quality specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 14.3 The proposed architecture operates at a frequency of 201.060MHz, when synthesised for Xilinx Virtex-IV series field programmable gate array.