Hardware IP Protection During Evaluation Using Embedded Sequential Trojan

摘要

REUSE-BASED SYSTEM-ON-CHIP (SoC) design using hardware Intellectual Property (IP) cores has become a pervasive practice in the industry to realize bug-free complex SoCs under aggressive time-to-market target 1. These IP cores usually come in the form of synthesizable Register Transfer Level (RTL) descriptions (Soft IP), or gate-level designs directly implementable in hardware (Firm IP), or GDS-II design database (Hard IF). During the life-cycle of an integrated circuit (IC), these IPs are vulnerable to various security issues as shown in Figure 1(a). The cost of IP infringement in the United States was estimated to be crossing $1 billion per day in 1998 2 with a large contribution coming from hardware IPs. These IPs are highly vulnerable to piracy issues at different stages. Other security threats include reverse-engineering efforts to facilitate cloning, counterfeiting, or remarking of ICs as well as malicious alterations by untrusted third-party vendors. Existing solutions to protect IPs from piracy and reverse-engineering include passive defenses like watermarking 1 as well as active defenses like encryption (coupled with requirement to use vendor-specific tools) 9, hardware metering 7, and obfuscation 12.