Intelligent vehicles are mobile robots on highways. They are expected to improve the safety, efficiency and environmental impacts of the current highway traffic systems. Vision systems will play an important role as sensors for the intelligent vehicles. This paper first compares the vision sensors with other sensing methods from an application point of view and then describes two vision systems, one which we have developed and another which we are developing. Two important features are required for the vision systems applied to intelligent vehicles: three-dimensional (3D) measurement capability and real-time operation. We chose a trinocular stereo vision scheme among a number of 3D vision processing methods because it is suitable for real-time operations with dedicated processor architectures. The trinocular stereo algorithm requires a large number of operations, but all the operations are relatively straightforward and, therefore, they are suitable for custom architecture implementation. The system takes three images simultaneously by using three TV cameras installed on a single horizontal line at the front grill of the test car. Vertical edges are extracted from these images and the spatial offsets (or disparities) among the images are calculated for measuring the distances to the objects. The first version was developed and installed in a car for highway testing. Two custom digital processors were developed: one for edge detection and the other for stereo matching. The test results were encouraging and the architectures based on ASIC (Application Specific Integrated Circuits) are 800 and 550 times more efficient, respectively, compared with conventional microprocessors for edge detection and stereo matching. The second version is currently being developed in order to further reduce the silicon area size. It uses hybrid analog/digital circuit technology while the first version uses only digital circuits. We are developing a hybrid analog/digital array processor chip which includes a large number of processing elements. Each processing element includes a digital memory unit, a data flow control switch unit and an analog arithmetic/logic unit. The analog arithmetic/logic unit reduces the silicon area size significantly compared with the digital one. The data flows among multiple processing elements in the array chip in a form of analog voltage. The data flow is controlled by the data flow switches. The digital memory unit controls the set-up of the data flow control switch and arithmetic/logic units.
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