THE DRIVING FORCE behind current IC fabrication technology is the demand for circuit complexity and density. A challenge common to process engineers and circuit designers in trying to meet this demand is the effect of process variation (PV) on design characteristics such as functionality and performance. PV is the deviation of parameters from desired values due to the limited controllability of a process. Every process has some level of uncertainty in its device parameters. As device size continues to scale down into the ultra-deep-submicron regime (less than 100 nm), manufacturing tools are less reliable in their control of design parameters. PV usually arises from limitations imposed by the laws of physics, imperfect tools, and properties of materials that are not fully comprehended. Sources of PV include random dopant fluctuation, annealing effects, and lithographic limitations. Typical variations are 10percent to 30percent across wafers and 5percent to 20percent across dies, and such variations can change the behavior of devices and interconnects. (See the "Related work" sidebar for a discussion of the various methods researchers have developed to deal with process variation.) Measuring the variation of each design or fabrication parameter is infeasible from a circuit designer's perspective. Therefore, we propose a methodology that approaches PV from a test perspective. This methodology advocates testing dies for process variation by monitoring parameter variations across a die and analyzing the data that the monitoring devices provide. We use ring oscillators (ROs) to map parameter variations into the frequency domain. Our use of ROs is far more rigorous than in standard practices. To keep complexity and overhead low, we neither employ analog channels nor use zero-crossing counters. Instead, we use a frequency domain analysis because it allows compacting RO signals using digital adders (thereby also reducing the number of wires), and decoupling frequencies to identify high PVs and problematic regions.
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