A Modified Integrated Circuit Interface Based on M-ary Digital Pulse Cycle Modulation

摘要

A modified integrated circuit interface based on M-ary digital pulse cycle modulation is proposed in this study by describing its principle and structure to reduce the complexity of a high-speed circuit design and to improve the data transfer rate of a bandwidth-limited system. A demonstration system is built by using Field Programmable Gate Array (FPGA) to simulate the transceiver functions in a bandwidth-limited RS232 bus with a maximum data transfer rate is 320 Kbps and the interface proposed is used to achieve the maximum data transfer rate of more than 1.1 Mbps, without any other change in hardware circuit. Experimental results indicate that the interface proposed can be used to achieve a better data transfer performance.