WITH CONTINUED TECHNOLOGY scaling, silicon is becoming increasingly less predictable. Recent years have brought an acceleration of wear-out mechanisms, such as oxide breakdown and negative bias temperature instability (NBTI), which occur over a part's lifetime. Researchers expect manufacturing device failure rates to increase significantly with decreases in device sizes, possibly reaching one in thousands or even hundreds of devices. Process variations will increase significantly in future technologies because fundamental laws of physics drive certain parametric variations, such as random dopant fluctuation (RDF) and line edge roughness, making their increased contribution to variability almost inevitable. In fact, Chen recently described extreme variations due to RDF and line edge roughness as fundamental barriers to controlling device parameters. The combination of wear-out mechanisms, RDF, and line edge roughness leads to an unpredictable silicon fabric that poses a major obstacle to reliable computing in future technologies. Evidence of this trend's importance is the occurrence of the word "variability" a staggering 73 times in the "Design" chapter of the 2005 International Technology Roadmap for Semiconductors (http://public.itrs.net). Researchers have proposed a range of circuit techniques and design methodologies to combat process variability effects (see the "Related work" sidebar), but these solutions are largely ad hoc and sparsely used in industry.
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