Low power SoC technology, which realizes ubiquitous computing era, is investigated. Low voltage operdion of 0.5V for logic and memory IPs and 1.0V operation for analog IP are target techniques. Such low voltage logic, memory and analog IPs are to be implemented in a single chip to realize super low power SoC. We have developed Self-Adjusted Forward Body Bias Technique to achieve low voltage operation of logic circuit, V-driver circuit to reduce power of bus, and high speed ADC which includes compensation circuit of device fluctuation.
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