A VARIETY OF yield-learning techniques are essential since no single approach can effectively find every manufacturing perturbation that can lead to yield loss. Test structures, for example, can range from being simple in nature (combs and serpentine structures for measuring defect-density and size distributions) to more complex, active structures that include transistors, ring oscillators, and SRAMs. Test structures are designed to provide seamless access to a given failure type: its size, its location, and possibly other pertinent characteristics. But their downside is that they cannot be sold for profit, hence, they are typically relegated to the wafer scribe lines, or limited to a small number of wafer lots, and are small in size. These characteristics of test structures are also a source of disadvantage. Specifically, because test structures are not extremely large, they cannot mimic the layout diversity actually found in production ICs. Also, because their volume is limited, their "sampling" of the fabrication process is somewhat bounded.
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