TECHNOLOGY SCALING will continue to follow Moore's law, letting designers use billions of transistors. But variability and reliability will be the barriers to future scaling, just as the barriers today stem from power and energy consumption. Die size, chip yields, and design productivity have thus far limited transistor integration in VLSI designs. But the focus is shifting to energy consumption, power dissipation, and power delivery. Transistor subthreshold leakage continues to increase, and there are leakage avoidance, tolerance, and control techniques for circuits. However, as technology scales further, new challenges will emerge, such as variability, single-event upsets, and device degradation. These problems will inevitably lead to inherent unreliability in components, posing serious design and test challenges. This problem is not new. Even today, systems design takes into account variability and reliability issues--for example, error-correcting codes in memories to detect and correct soft errors. We cope with variability in transistor performance through careful design, as well as testing for frequency binning. But with continued technology scaling, the impact of these issues is becoming greater, and we must devise techniques to deal with them effectively.
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