A 10bit 30MSample/s low-power pipelined A/D converter using a pseudo differential architecture

摘要

A 10b 30MS/s low-power CMOS pipeline A/D converter(ADC) is described, The ADC using a pseudo differential architecture with a capacitor cross-coupled sample-and-hold(S/H) circuit consumes only 16mW with a single 2.0V supply. The chip is fabricated in a standard O.3-μm 2-poly 3-metal CMOS technology. The ADC achieves the signal-to-noise-and-distortion ratio(SNI)R) of 54dB at Nyquist.