OVER THE YEARS, on-die cache capacity has increased with every new generation of processor designs. Meanwhile, six-transistor (6T) SRAM continues to be the workhorse of cache memory in high-performance CPUs. Figure 1 shows the scaling trend of cache memory capacity in high-performance CPUs from 130 nm to 32 nm. Designers have continually increased on-die cache size to meet growing memory bandwidth requirements. Relentless transistor scaling and enhanced transistor performance have allowed ever-increasing cache memory capacity and performance to keep up with CPU performance needs. Large cache memory typically consists of SRAM because of its speed and high compatibility with logic transistor technology. Technology scaling has made it feasible to integrate more than 30 Mbytes of high-speed SRAM cache memory at the 32-nm logic technology node. Further advancements in logic transistor technology will continue to impact SRAM performance and density, and mitigate many key scaling challenges facing 6T SRAM.
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