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Logic design for printability using OPC methods

机译:Logic design for printability using OPC methods

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摘要

abstract_textpThis article provides an intriguing analysis of traditional DFM techniques and describes methods of extending them into post-tapeout optimization in the form of OPC or RET design for printability. Layouts are altered so that lithographic patterning control improves. A highlight of the article is its subsequent analysis of the implementation feasibility of actual product designs.This article provides an intriguing analysis of traditional DFM techniques and describes methods of extending them into post-tapeout optimization in the form of OPC or RET design for printability. Layouts are altered so that lithographic patterning control improves. A highlight of the article is its subsequent analysis of the implementation feasibility of actual product designs./p/abstract_text

著录项

  • 来源
    《ieee design & test of computers》 |2006年第1期|30-37|共8页
  • 作者单位

    Freescale Semicond, Tech Staff, F-38926 Crolles, France;

    Freescale Semicond, OPC Work, Austin, TX USA;

    Freescale Semicond, Crolles2 Alliance Design Proc Buffer Team, F-38926 Crolles, FranceFreescale Semicond, Crolles2 Alliance Design Manual Grp, F-38926 Crolles, France;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 英语
  • 中图分类
  • 关键词

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