Panel Summaries: Infrastructure IP design for repair in nanometer technologies

摘要

AS TECHNOLOGIES ADVANCE and semiconductor process dimensions shrink into the nanometer and subnanometer range, a high degree of sensitivity to defects begins to impact overall yield and quality. Achieving better yield and higher quality requires innovative structures and techniques to collect, analyze, and fix problems. A special session at the Second IEEE International Workshop on infrastructure IP, held in conjunction with the International Test Conference (28 to 29 October 2004 in Charlotte, North Carolina), focused off solutions related to yield at various levels, from processes to design implementation.