Construction and Verification of PLC LD Programs by the LTL Specification

摘要

An approach to the construction and verification of LD programs of programmable logic controllers (PLC) for discrete problems is proposed. The specification of the program behavior is performed using the linear temporal logic language (LTL). Programming is performed using the Ladder Diagram (LD) language by the LTL specification. The correctness analysis of the LTL specification is performed using the Cadence SMV symbolic model-checking tool. An approach to programming and verifying the PLC LD programs is shown using an example. The LD program, its LTL specification, and an SMV model are given for a discrete problem. This article is aimed at the description of an approach to PLC programming that will provide the correctness analysis of PLC LD programs using the model-checking method. Therefore, the variation in each programmable variable is described using a pair of LTL formulas. The first LTL formula describes situations in which the corresponding variable increases and the second LTL formula specifies conditions leading to a decrease in the variable. LTL formulas, which are considered to specify the behavior of variables, are constructive in the sense that the PLC program corresponding to the temporal properties expressed by these formulas is constructed by them. Thus, PLC programming is reduced to the construction of the LTL specification for the behavior of each programmed variable. In addition, the SMV model of the PLC LD program is constructed by the LTL specification. Then, the SMV model is analyzed for correctness (relative to additional conventional general-programming LTL properties) by the Cadence SMV symbolic model-checking tool.