Test case generation from formal system specifications based on UML State Machines

摘要

A comprehensive test is needed for the validation of industrial systems especially embedded devices. In particular the testing of the behaviour of the implemented system against its specified behaviour is of crucial importance. The manual creation of test cases is time consuming, difficult and error-prone for complex specifications. Therefore a method for the automatic generation of test cases from the specification is suggested in this paper. The basis of this method is the formalized specification of the required behaviour with UML State Machines. The UML State Machine is a result of a top-down-design of a development process with technical constraints. This paper briefly describes the mapping of the characteristic UML State Machine elements, e.g. state, pseudo state, transition, guard and action, on an Extended Safe Place/Transition Net (ESTPN). Based on an ESPTN, well-known methods of the Petri Net theory can be applied and a test case generation is possible.