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机译:An Advanced Finite Element Model for BiCMOS Process Oriented Ultra-Thin Wafer Deformation
Tech Univ Dresden, Chair Circuit Design & Network Theory, D-01062 Dresden, Germany;
IHP Leibniz Inst Innovat Mikroelekt, Dept Technol, D-15236 Frankfurt, Germany|Tech Univ Berlin, Dept Elect Engn & Comp Sci, D-10587 Berlin, Germany;
IHP Leibniz Inst Innovat Mikroelekt, Dept Technol, D-15236 Frankfurt, Germany|Sabanci Univ, Fac Engn & Nat Sci FENS, TR-34959 Istanbul, TurkeyIHP Leibniz Inst Innovat Mikroelekt, Dept Technol, D-15236 Frankfurt, Germany;
BiCMOS process; ultra-thin wafer; stress modeling; wafer warping; finite element analysis (FEA);