A new automated design and optimization method of CMOS logic circuits based on Modified Imperialistic Competitive Algorithm

摘要

This paper proposes a novel evolutionary approach based on modified Imperialist Competitive Algorithm for combinational logic circuits designing and optimization. The Imperialist Competitive Algorithm operates on real values and is not applicable to logic circuits optimization problems. So a modified version of ICA is proposed to overcome this shortcoming. Modification of the algorithm depends on random cell replacement between Imperialist and its colonies as assimilation policy. Also a multi-objective evaluation mechanism in the form of a weighted cost function is introduced to obtain optimized circuits in case of circuit area and propagation delay. To evaluate the effectiveness of this method some general benchmark circuits are used in which the circuits with fewer logic cells (minimized space) and lower propagation delay are obtained. The simulation results of our proposed method are compared with some conventional and heuristic methods. Simulation results show that our proposed method significantly improves the performance factor which represents both circuit area and propagation delay.