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首页> 外文期刊>Journal of the Chinese Institute of Engineers >An improved MASH sigma-delta modulator with all-anolog interstage and input-feedforward architecture
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An improved MASH sigma-delta modulator with all-anolog interstage and input-feedforward architecture

机译:一种改进的MASH SIGMA-DERTA调制器,具有全主体级联和输入馈电架构

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摘要

This paper puts forward an improved multi-stage noise-shaping (MASH) sigma-delta modulator. Derived from a fourth-order two-stage MASH architecture with adder-less architecture of cascade of integrators with feedforward (CIFF), the proposed modulator improves the method of extracting quantization noise of the first stage to form an all-analog interstage, and two input-feedforward paths are added to the second stage to reduce the output swing of the integrator. Analyses and measurements indicate that the proposed architecture has lower in-band quantization noise power, higher signal-to-quantization noise ratio (SQNR), and lower power consumption and complexity as well. When operating from a 1.2 V supply, the modulator achieves 107.56 dB peak SQNR, 71.8 dB peak Signalnoise and distortion ratio while consuming 26 mW, with an OSR of 8 at a 160 MHz sampling frequency.
机译:本文提出了一种改进的多级噪声整形(MASH)sigma-delta调制器。该调制器源于四阶两级MASH结构和无加法器的前馈积分器级联结构(CIFF),改进了提取第一级量化噪声的方法,形成了全模拟级间结构,并在第二级增加了两条输入前馈路径,以减小积分器的输出摆幅。分析和测量表明,该结构具有较低的带内量化噪声功率、较高的信量化噪声比(SQNR)、较低的功耗和复杂度。当在1.2 V电源下工作时,调制器达到107.56 dB峰值SQNR、71.8 dB峰值信号噪声和失真比,同时消耗26 mW,在160 MHz采样频率下OSR为8。

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