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A Novel Approach to Analyze Testing of Nano On-Chip Networks

机译:一种分析纳米片网网络测试的新方法

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摘要

Test time of a test architecture is an important factor which depends on the architecture's delay and test patterns. Here a new architecture to store the test results based on network on chip is presented. In addition, simple analytical model is proposed to calculate link test time for built in self tester (BIST) and external tester (Ext) in multiprocessor systems. The results extracted from the model are verified using FPGA implementation and experimental measurements. Systems consisting 16, 25, and 36 processors are implemented and simulated and test time is calculated. In addition, BIST and Ext are compared in terms of test time at different conditions such as at different number of test patterns and nodes. Using the model the maximum frequency of testing could be calculated and the test structure could be optimized for high speed testing.
机译:测试体系结构的测试时间是一个重要因素,它取决于体系结构的延迟和测试模式。本文提出了一种基于片上网络的测试结果存储体系结构。此外,还提出了一个简单的分析模型来计算多处理机系统中内置自测试仪(BIST)和外部测试仪(Ext)的链路测试时间。从模型中提取的结果通过FPGA实现和实验测量进行了验证。实现和模拟了由16、25和36个处理器组成的系统,并计算了测试时间。此外,在不同的测试模式和节点数等条件下,比较了BIST和Ext的测试时间。利用该模型可以计算出测试的最大频率,并优化测试结构以进行高速测试。

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