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首页> 外文期刊>Journal of Physics, D. Applied Physics: A Europhysics Journal >Non-volatile reconfigurable spin logic device: parallel operations
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Non-volatile reconfigurable spin logic device: parallel operations

机译:非易失性可重新配置自旋逻辑设备:并行操作

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摘要

A new proposal is given for designing a non-volatile, completely spin logic device, that can be reprogrammed for different functional classical logical operations. We use the concept of bias driven spin dependent circular current and current induced magnetic field in a quantum ring under asymmetric ring-to-electrode interface configuration to implement all the Boolean operations. We extend our idea to build two kinds of parallel computing architectures for getting parallelized operations, all at a particular time. For one case, different kinds of parallel operations are performed in a single device, whereas in the other type all the possible inputs of a logic gate are processed in parallel and all the outputs are read simultaneously. The performance and reliability are investigated in terms of power, delay and power-delay-product and finally the system temperature. We find that both the individual and simultaneous logic operations studied here are much superior compared to the operations performed in different conventional logic families like complementary metal oxide semiconductor logic, transistor-transistor logic, etc. The key advantage is that we can perform several logic operations, as many as we wish, repeating the same or different logic gates using a single setup, which indeed reduces wiring in the circuits and hence consumes much less power. Our analysis can be utilized to design optimized logic circuits an nano-scale level.
机译:提出了一种设计非易失性、完全自旋逻辑器件的新方案,该器件可以针对不同的经典逻辑操作进行重新编程。我们使用偏置驱动的自旋相关环形电流和不对称环-电极界面配置下量子环中的电流感应磁场的概念来实现所有布尔运算。我们扩展了我们的想法,构建了两种并行计算体系结构,用于在特定时间实现并行操作。在一种情况下,不同类型的并行操作在单个设备中执行,而在另一种情况下,逻辑门的所有可能输入都并行处理,所有输出都同时读取。从功率、延迟和功率延迟积以及系统温度的角度研究了系统的性能和可靠性。我们发现,与互补金属氧化物半导体逻辑、晶体管-晶体管逻辑等不同传统逻辑系列中执行的操作相比,本文研究的单个逻辑操作和同时逻辑操作都要优越得多。关键的优势在于,我们可以执行多个逻辑操作,如我们所愿,使用单个设置重复相同或不同的逻辑门,这确实减少了电路中的布线,因此消耗的电力要少得多。我们的分析可用于设计纳米级的优化逻辑电路。

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