INVESTIGATION AND DESIGN OF RADIX-2~K FFT PROCESSORS FOR OFDMA SYSTEMS

摘要

In an OFDMA system, only part of input/output of IFFT/FFT for uplink/downlink is non-zero on a user equipment (UE) side. Hence, IFFT/FFT can be further simplified by utilizing the property. Without loss of generality, in this paper, we consider IFFT for uplink OFDMA, as a design and demonstration example. In this case, the number of nonzero input subcarriers is considerably less than the length of IFFT. As such, by eliminating computation on zero-input subcarriers, one can increase the computational efficiency of IFFT. Moreover, in hardware design, the area of processors is reduced by deleting unnecessary hardware units, such as memory, multipliers, and butterfly units. Also, we propose a radix-2~k pruned FFT combined with a time shift algorithm for consecutive partial inputs. This algorithm makes the proposed architectures more flexible for the need of different subcarrier allocations. An IFFT architecture for IEEE802.11ax WLAN standard is proposed, which is verified by implementing an 8-parallel 2048-point partial-input multi-path delay commutator (MDC) IFFT for 8 users using TSMC 90 nm process. Its area and power consumption are 0.589 mm~2 and 48.68mW, respectively, under 300MHz.