Design and Implementation of Variable Length FFT Processor for OFDMA System Using FPGA

摘要

For Orthogonal Frequency Division Multiple Access (OFDMA) system module, there is a need for an efficient alterable point FFT processor. Therefore, it is meaningful to design a FFT processor for which input data points could be alterable. In this paper the variable input FFT processor is designed to meet the requirements of OFDMA system. For this, in this paper we select the 2D Fourier transform algorithm as the kernel algorithm, VHDL language is used to present a detail design of two-stage pipeline structure, ModelSim (SE) for the simulation, and verify on the Spartan3E FPGA. Simulation results show that the way of implementation and design is right and meet the IEEES02.16e standard, at the same time the data precision is 16 bits, limits the clock frequency of 100MHz, the overall timing design stability , and it could reach the scope of real-time processing