Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC

摘要

In this paper a 4-bit 720 MHz low-power successive approximation register ADC is simulated in a 0.18 μm digital CMOS process. By using both of the 2-bit/step and time-interleaved techniques, a high sampling frequency is obtained. To simplify the SAR ADC in lowbit applications, the analog switches are eliminated and replaced with inherent digital switches of SAR logics. The power supply, resolution, sampling frequency, SNDR, and power consumption of the proposed SAR ADC are 1.8 V, 4-bit, 720 MHz, 22.1 dB, and 10 mW.