Automatic generation of an instruction-set level simulator with the ASIP development system PEAS-III

摘要

An automatic generation method of an instruction-set level simulator with the ASIP development system PEAS-III is proposed. In this method, the pipeline processor model which is used in PEAS-III is represented in a software language and the program derived from the model can he execute as a simulator for a given processor description. Since SystemC is the language for simulators in our method, modeling of pipeline stages as concurrent processes is easy. In addition, with the cycle-based simulation kernel enables accurate and shorter-time simulation for pipeline processors. Experimental results show that simulation time of our simulator for a processor generated with PEAS-III is around 7 times shorter than a VHDL simulator's.