A VLSI architecture for shape-adaptive discrete cosine transformer dedicated to MPEG-4 video codec

摘要

In this paper a VLSI architecture of the SA-DCT is described, which can be employed dedicatedly for MPEC-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. The proposed SA-DCT core is integrated with 40.000 gates by using 0.35μm triple-metal CMOS technology, which operates at 20 MHz, and hence enables the realtime codec of CIF (352×285 pixels) pictures.