A chip set for LSI test systems

摘要

A chip-set for 20-MHz digital LSI test systems was developed. The chipset consists of 5-custom LSIs, 2 for per-pin timing generators, 3 for pin-electronics and DA converter. To realize a tester-in-test-head, the chip count and power consumption must be minimized. A new timing vernier and a 1 μm standard CMOS process were utilized for timing generators Though a CMOS process enables low power consumption, cross talk and thermal characteristics might be sacrificed. High accuracy analog IC designs were the solutions to the problems. Per-pin-DC-measure functions were also integrated in a chip to obtain a high test- throughput. A new trimless DA converter was also developed for pin-electronics settings. This 28-channel 12.7 bit DAC is also fabricated using the 1 μm standard CMOS process.