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Wafer-Scale Arrays of Nonvolatile Polymer Memories with Microprinted Semiconducting Small Molecule/Polymer Blends

机译:带有微印半导体小分子/聚合物共混物的非易失性聚合物记忆体的晶圆级阵列。

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Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropattems of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate /bottom- contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropattems of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface.
机译:具有溶液处理的铁电聚合物的非易失性铁电栅场效应晶体管(Fe-FET)存储器备受关注,因为它们有潜力用于低成本的柔性器件中。特别地,开发具有机械柔性的用于对高性能半导体沟道层进行构图的工艺不仅对于适当的单元间隔离而且对于柔性非易失性存储器的阵列都是必不可少的。我们展示了一种用于印刷溶液处理的半导体小分子/绝缘聚合物共混物的大型微型图案的稳健路线,用于非易失性铁电聚合物存储器的高性能阵列。非易失性存储器件基于具有铁电聚合物绝缘体和微图案化半导体混合通道的顶栅/底接触式Fe-FET。薄混合半导体薄膜的印刷微图案是通过我们的选择性接触蒸发印刷获得的,其中与微图案弹性体聚二甲基硅氧烷(PDMS)模具接触的半导体小分子优先蒸发并吸收到PDMS模具中,同时绝缘聚合物保持完整。在4英寸晶圆上的很大面积上很容易开发出具有各种形状和尺寸的清晰定义的微米级图案,从而可以制造具有高度均匀的器件性能的Fe-FET的大规模印刷阵列。我们从统计角度分析了Fe-FET的存储特性,包括开/关比,工作电压,保持力和耐用性,它们是半导体薄膜微图案尺寸的函数。此外,通过成功地将印刷有挠性基板的带有瞬态粘合剂层的大面积Fe-FET从硬质基板上分离出来,然后将其转移到非平面表面上,从而产生了上卷式存储阵列。

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