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首页> 外文期刊>Journal of The institution of engineers (India), Series C >Mission Management Computer and Sequencing Hardware for RLV-TD?HEX-01 Mission
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Mission Management Computer and Sequencing Hardware for RLV-TD?HEX-01 Mission

机译:Mission Management计算机和RLV-TD的测序硬件?HEX-01任务

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AbstractReusable Launch Vehicle-Technology Demonstrator Hypersonic Experiment (RLV-TD HEX-01) mission posed some unique challenges in the design and development of avionics hardware. This work presents the details of mission critical avionics hardware mainly Mission Management Computer (MMC) and sequencing hardware. The Navigation, Guidance and Control (NGC) chain for RLV-TD is dual redundant with cross-strapped Remote Terminals (RTs) interfaced through MIL-STD-1553B bus. MMC is Bus Controller on the 1553 bus, which does the function of GPS aided navigation, guidance, digital autopilot and sequencing for the RLV-TD launch vehicle in different periodicities (10, 20, 500?ms). Digital autopilot execution in MMC with a periodicity of 10?ms (in ascent phase) is introduced for the first time and successfully demonstrated in the flight. MMC is built around Intel i960 processor and has inbuilt fault tolerance features like ECC for memories. Fault Detection and Isolation schemes are implemented to isolate the failed MMC. The sequencing hardware comprises Stage Processing System (SPS) and Command Execution Module (CEM). SPS is ‘RT’ on the 1553 bus which receives the sequencing and control related commands from MMCs and posts to downstream modules after proper error handling for final execution. SPS is designed as a high reliability system by incorporating various fault tolerance and fault detection features. CEM is a relay based module for sequence command execution.]]>
机译:<![cdata [ <标题>抽象 ara id =“par1”>可重复使用的启动车辆技术示范器超声实验(RLV- TD Hex-01)任务在航空电子硬件的设计和开发中提出了一些独特的挑战。这项工作提出了使命关键航空电子硬件的细节主要是使命管理计算机(MMC)和排序硬件。 RLV-TD的导航,指导和控制(NGC)链是双冗余,具有通过MIL-STD-1553B总线接口的交叉划分的远程端子(RTS)。 MMC是在1553总线上的总线控制器,该总线控制GPS辅助导航,指导,数字自动自动驾驶仪和RLV-TD发射车辆在不同的周期(10,20,500?MS)中的函数。在MMC中的数字自动驾驶仪执行,周期性为10?MS(在上升阶段)是第一次引入并在飞行中成功演示。 MMC由Intel I960处理器围绕Intel I960处理器构建,具有内置的容错功能,如ECC进行记忆。实现故障检测和隔离方案以隔离失败的MMC。测序硬件包括阶段处理系统(SPS)和命令执行模块(CEM)。在1553总线上,SPS是“RT”,该总线是在适当的错误处理后从MMCS和POST到下游模块接收测序和控制相关命令。通过合并各种容错和故障检测功能,SPS设计为高可靠性系统。 CEM是基于继电器的模块,用于序列命令执行。 ]]>

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