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首页> 外文期刊>Journal of systems architecture >Task mapping and scheduling for network-on-chip based multi-core platform with transient faults
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Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

机译:基于网络的基于网络的多核平台的任务映射和调度,具有瞬态故障

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Technology scaling has enabled the integration of large number of transistors into a single chip, leading to performance enhancement via incorporation of Processing Elements (PEs), Intellectual Property (IP) cores and Memory Units together on the same platform. On the downside, it has led on-chip components to be more susceptible to faults, both permanent and transient. Permanent faults are predictable in nature and can be dealt with at the time of manufacturing or in field using spares/redundancy. Transient faults also adversely affect the application performance but are unpredictable in nature. Handling transient faults is a challenging task, especially in a real-time system where different applications are executed with various timing constraints. Although significant amount of work has been reported in literature for transient fault management, it lacks addressing the temporal constraint satisfaction of the tasks while restricting the energy expenditure of the system. Existing fault tolerant policies do task replication to ensure higher percentage of deadline satisfaction but at the cost of higher energy consumption. Checkpointing approach can make energy consumption low, however, the number of tasks satisfying their timing constraint also becomes low. Thus a fault tolerant policy which could jointly address the timing and energy constraint in a real time system is desirable. This work proposes an algorithm to intelligently perform a fault-tolerant resource allocation in real-time dynamic scenarios where tasks of applications are not known apriori. The slack times of the incoming tasks have been exploited in the application mapping/scheduling phase of the algorithm, to assign a fault tolerant policy to the corresponding task for mitigating the effect of transient faults. This helps to improve the deadline satisfaction of the task and also reduce the energy consumption. While comparing with existing works, the proposed algorithm achieves 19.8%, 43.5% and 85.8% im
机译:技术缩放使大量晶体管集成到单个芯片中,通过在同一平台上将处理元素(PES),知识产权(IP)核和内存单元结合到具有性能增强。在缺点方面,它引出了片上部件,更容易受到故障,永久性和瞬态。永久性故障本质上可预测,可以在制造或使用备件/冗余的情况下处理。瞬态断层也对应用程序性能产生不利影响,但本质上是不可预测的。处理瞬态故障是一个具有挑战性的任务,尤其是在使用各种时序约束执行不同应用程序的实时系统中。虽然在文献中报告了瞬态故障管理的大量工作,但缺乏解决任务的时间约束满足在限制系统的能源支出时。现有的容错策略进行任务复制,以确保截止日期满意度的更高百分比,但能耗更高的成本。检查点的方法可以使能量消耗低,但是,满足其定时约束的任务数量也变低。因此,可以共同解决实时系统中的定时和能量约束的容错策略是理想的。这项工作提出了一种算法,可以在实时动态方案中智能地执行容错资源分配,其中应用程序的任务不是已知的apriori。在算法的应用程序映射/调度阶段,传入任务的松弛时间已被利用,以将容错策略分配给相应的任务,以减轻瞬态故障的影响。这有助于提高任务的截止日期满意度,并降低能耗。在与现有作品相比,所提出的算法达到19.8%,43.5%和85.8%

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