Improving the Verification of Real-Time Systems Using Time Petri Nets

摘要

Formal verification methods using Time Petri Net have called the attention of researchers and practitioners in real-time systems design during the last two decades. Special attention was dedicated to methods that could be integrated to the design process since the very beginning, that is, in the requirement phase. However, real-time systems requirements are always concerned with quantitative temporal properties, and therefore, a verification technique should give some feedback on target values for these properties. This paper presents an alternative algorithm - based on reachability - to treat the real-time verification of discrete systems. The proposed method is based on an enumerative technique to generate the complete state space that has some advantages - since it has to be done only once - and disadvantages - since the process is combinatorial. However, our proposal leads to better results when compared to other available techniques, especially to complex problems, besides being able to evaluate quantitative and qualitative properties in the same process. Timed Computation Tree Logic is used as specification language, and Timed Transition Graph (TTG) is introduced to represent system functional behavior. A new algorithm is proposed to build a TTG and applied to a case study to illustrates the operation of the proposed algorithm.