A Multi-Time-Step Transmission Line Interface for Power Hardware-in-the-Loop Simulators

摘要

Developing a general and stable numerical interface for power hardware-in-the-loop (PHIL) applications is a major challenge. This paper proposes a stable, robust and precise implementation of a multi-time-step interface for a PHIL simulator based on the Bergeron transmission line model (BTLM). Two limitations of the transmission-line-based interface were identified, and remedial strategies were formulated in order to ensure that the interface was compatible with the PHIL application. Stability and passivity analyses were then conducted on the resulting interface to verify its performance. The proposed interface was implemented in an experimental 3-kVA PHIL setup, using a custom-made switching power amplifier (PA). Multiple tests were performed in order to demonstrate the stability and accuracy of the closed-loop system under a wide range of operating conditions and with various devices under test (DUTs). Experimental results were obtained from islanding tests involving different simulated load configurations and solar inverter responses to network disturbance while operating in a closed-loop configuration.