Secondary CLIQ, a robust, redundant, and cost-effective means of protecting high-field accelerator magnets

摘要

Secondary CLIQ is a quench protection method for protecting high-field accelerator magnets that involves charged capacitors into secondary normal-conducting coils that are magnetically coupled to the superconducting coils. The resulting coupling losses quickly brings the magnet to normal state and safely discharges it. No direct electrical or thermal link is required between the primary and secondary coils, and robust insulation is placed in between them. The two secondary circuits per magnet are galvanically insulated from the primary circuit, so that the tens to hundreds of CLIQ units needed to protect an accelerator circuit are galvanically insulated from one-another and from the superconducting magnets. The two secondary circuits per magnet each feature a CLIQ unit, and each CLIQ unit discharge is sufficient to bring the magnet to normal state over the entire operational current range. The coil geometry is such that the CLIQ discharge does not raise the voltage over the half-turns of the superconducting coils. After the superconducting coils develop resistance, a significant fraction of the stored magnetic energy is inductively transferred to and dissipated in the secondary coils. The resulting favourable adiabatic hot-spot temperature and voltage-to-ground enables the magnet designer to reduce the copper content of the superconducting coils, and thus lower the overall cost of the magnet. Secondary CLIQ quench simulations were performed on a hypothetical 14 m variant of the HD2 Nb3Sn dipole with a bore field of 16 T. It is demonstrated that the Secondary CLIQ method protects the magnet over its entire operational current range even in the case where one of the two CLIQ units fails to discharge with an adiabatic hotspot temperature of 248 K and voltage-to-ground of 610 V under nominal protection conditions, and a worst-case adiabatic hot-spot temperature of 263 K and voltage-to-ground of 840 V under fault conditions.