AN AUTOMATED METHODOLOGY FOR LOGIC CHARACTERIZATION VEHICLE DESIGN

摘要

Due to the high complexity of emerging technology nodes, fast yield ramping to shorten time-to-market is an incredible challenge. Meeting this challenge requires a design and fabrication methodology that enables yield learning to be accomplished using actual silicon structures and chips. Many types of test structures exist, ranging from passive styles (e.g., via arrays and comb drives) to large, complex circuits (e.g., ring oscillators and SRAM). However, only a product-like test chip includes all the logic characteristics of an actual customer design. Fabrication and test of product-like test chips is a common practice for fabless companies, foundries, and integrated device manufacturers.