Tuning Parallelism of Sequential Applications via Thread Level Speculation for Chip Multiprocessors

摘要

Thread level speculation (TLS) has been researched recently as a parallel mechanism pursuing high performance for chip multiprocessors. However, there are three remaining bottlenecks limiting the CMP utility to parallelize sequential applications: unpredictable control flow, indirect data access, and input-dependent parallelism. This paper presents a CMP hardware simulation system with TLS support, and a convenient programming model. A sequential code can be easily transformed to a TLS one. With the system's hotspots analysis, draft TLS codes can be adjusted to a higher level parallelism. Then with the assistance of profiling or runtime information, we can tune the applications from different aspects. According to the experiment, the three bottlenecks have been well addressed. With step-by-step TLS programming, the benchmarks' average speedups are 7%, 22%, and 126%, respectively.