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首页> 外文期刊>International Journal of Computational Science and Engineering >Enhancing the performance of process level redundancy with coprocessors in symmetric multiprocessors
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Enhancing the performance of process level redundancy with coprocessors in symmetric multiprocessors

机译:在对称多处理器中增强与协处理器的过程级冗余的性能

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摘要

>Transient faults are rising as a crucial concern in the reliability of computer systems. As the emerging trend of integrating coprocessors into symmetric multiprocessors, it offers a better choice for software-oriented fault tolerance approaches. This paper presents coprocessor-based process level redundancy (PLR) which makes use of coprocessors and frees CPU cycle to other tasks. The experiment is conducted by comparing the performance of one CPU version of PLR and one coprocessor version PLR using a subset of optimised SPEC CPU2006 benchmark. It shows that the proposed approach enhances performance by 32.6% on average. The performance can be enhanced more if one application contains more system calls. This common technique can be adapted to other software-based fault tolerance as well.
机译:>瞬态故障是计算机系统可靠性关注的关注。 作为将协处理器集成到对称多处理器的新出现趋势,它为软件导向的容错方法提供了更好的选择。 本文介绍了基于协处理器的流程级冗余(PLR),它利用协处理器和释放CPU周期到其他任务。 通过使用优化规范CPU2006基准测试的子集比较PLR和一个协处理器版本PLR的一个CPU版本的PLR和一个协处理器版本的性能来进行实验。 它表明,拟议的方法平均增强了32.6%的性能。 如果一个应用程序包含更多系统调用,则可以提高性能。 这种常用技术也可以适应其他基于软件的容错。

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