A 12-b Low-Voltage CMOS Pipelined Analog-to-Digital Converter Without Digital Error Correction Technique

摘要

A 12-b 40-MS/s low power pipelined CMOS analog-to-digital converter without digital error correction technique is designed and implemented. A novel switched-capacitor multiply-by-two amplifier with an accurate gain of two is proposed for pipelined ADC. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.38 LSB and 0.45 LSB respectively, while SNDR is 67.5 dB and SFDR is 75.6 dB at an input frequency of 10 MHz. Operating at 40 MS/s sampling rate under a single 1.5 V power supply, the power consumption is 68.2 mW in a 0.35 μm CMOS process.