Adaptive Resolution of Digital Pulse Width Modulation for Switching Power Converters

摘要

This paper demonstrates an adaptive resolution digital pulse-width-modulation (DPWM) control of switching power converters. Typically switching power device use pulse width modulation (PWM) as the control scheme for regulation, which is more suitable for a high speed digital controller. An interesting control solution to reduce the clock spurs of the PWM uses the noise shaping characteristics of the delta-sigma (Δ-∑) modulator. Efficient DPWM controller implementations improve the system stability issues unique to digital control. This paper proposes an adaptive low to high-resolution of Digital-PWM (DPWM) architecture for low-power Switching Mode Power Supply (SMPS). Adaptive resolution of ADC is introduced as a digital source to increase the flexible effective DPWM resolution, thus enhancing limit cycling, and enabling low-power, small-area DPWM implementations. The proposed DPWM takes advantage of Digital Clock Manager (DCM) phase-shift characteristics which is available in high speed digital circuit and combines a counter-comparator with a Multi-stage-noise-Shaping (MASH) Delta-Sigma (Δ-∑) modulator. Utilizing the selectable frequency regulator to optimization of ADC resolution, we can switch to the high-resolution ADC speed up the feedback time when system tends to be unstable, or the meduim-resolution ADC to eliminate the power consumption when the system is stable. Three kinds of resolutions including 11-bit, 13-bit and 17-bit effective prototype DPWM along with a digital PID control algorithm are verified by using a Xilinx Spartan-3E FPGA on a discrete low-power buck converter. Experimental results with constant switching frequency up to 4 MHz validate the functionality of the proposed DPWM. Three experimental buck converters will be developed to illustrate different aspects of this work. Simulations are used to further corroborate the results. This Adaptive approach can not only obtain a high-resolution DPWM while reducing system clock frequency, but also enhance the efficiency to the system by tuning ADC resolution to against different incoming noise.