A Clock Oscillator Synchronized with a Power Network

摘要

A circuit of a clock oscillator is proposed, whose frequency and phase are synchronized with an industrial 50-Hz power network. The synchronization with the network reduces the effect of network-interference impact on signals of low-power sensors during their reproduction, measurement, and processing. The device, which was built using several STTL chips, is a frequency multiplier that is based on a phase-synchronization system with a frequency divider in the feedback loop. Due to the phase-frequency principle of the error-signal formation, the danger of capture at multiple frequencies is eliminated and an extended synchronization band is achieved without parasitic frequency modulation of the generated pulses. The device is powered with a +5-V source and has a synchronization band of +/- 25% of the rated network frequency. The frequency multiplying factor, which in the described embodiment is 65536 (the clock frequency is 3276.8 kHz), can be set arbitrarily via a conjugate change of the frequency-divider modulus and the oscillator center frequency.