Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems

摘要

FinFET based Improved Pass-transistor Adiabatic Logic (IPAL) powered by four-phase power-clock is presented. Capable of operating across MHz to GHz frequency range, it consists of differential cascode structure along with discharge devices for increased energy efficiency, lower leakage and switching transients, and glitch free output. Use of FinFET eliminates limitations of MOS device. IPAL is validated for energy efficiency through combinational and sequential circuits using 2N2P, 2N2N2P and Positive Feedback Adiabatic Logic circuits. Design of IPAL, energy modelling and performance characteristics are presented. Cyclic Redundancy Check architecture being a commonly used methodology to detect errors in data transmission and reception in communication protocols, 32-bit CRC circuit has been designed and performance metrics are analysed. CRC architecture designed using FinFET based IPAL circuit has been compared against FinFET based 2N2P, 2N2N2P and PFAL adiabatic circuits. 30 nm FinFET Verilog-A models have been used for designs in Cadence (R) environment. Energy efficiency of 24%, 41% and 48% have been attained against 2N2P, 2N2N2P and PFAL based 32-bit CRC architectures while operating at 500 MHz. (C) 2019 Elsevier GmbH. All rights reserved.