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Predicting HPC parallel program performance based on LLVM compiler

机译:基于LLVM编译器预测HPC并行程序性能

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Performance prediction of parallel program plays key roles in many areas, such as parallel system design, parallel program optimization, and parallel system procurement. Accurate and efficient performance prediction on large-scale parallel systems is a challenging problem. To solve this problem, we present an effective framework for performance prediction based on the LLVM compiler technique in this paper. We can predict the performance of a parallel program on a small amount of nodes of the target parallel system using this framework toned but not execute this parallel program on a corresponding full-scale parallel system. This framework predicts the performance of computation and communication components separately and combines the two predictions to achieve full program prediction. As for sequential computation, we first combine the static branch probability and loop trip count identification and propose a new instrumentation method to acquire the number of each instruction type. We then construct a test program to measure the average execution time of each instruction type. Finally, we utilize the pruning technique to convert a parallel program into a corresponding sequential program to predict the performance on only one node of the target parallel system. As for communication, we utilize the LogGP model to model point-to-point communication and the artificial neural network technique to model collective communication. We validate our approach by a set of experiments that predict the performance of NAS parallel benchmarks and CGPOP parallel application. Experimental results show that the proposed framework can accurately predict the execution time of parallel programs, and the average error rate of these programs is 10.86%.
机译:并行程序的性能预测在许多领域扮演密钥角色,例如并行系统设计,并行程序优化和并行系统采购。大规模并行系统的准确高效性能预测是一个具有挑战性的问题。为了解决这个问题,我们对本文基于LLVM编译技术提供了一种有效的性能预测框架。我们可以使用该框架预测对目标并行系统的少量节点的并行程序对目标并行系统的少量节点的性能,但未在相应的全尺度并行系统上执行该并行程序。该框架分别预测计算和通信组件的性能,并结合了两个预测来实现完整的程序预测。对于顺序计算,我们首先将静态分支概率和循环跳闸计数标识结合起来,并提出一种新的仪器方法来获取每个指令类型的数量。然后,我们构建一个测试程序来测量每个指令类型的平均执行时间。最后,我们利用修剪技术将并行程序转换为相应的顺序程序,以预测仅目标并行系统的一个节点上的性能。至于通信,我们利用LOGGP模型来模拟点对点通信和人工神经网络技术来模拟集体通信。我们通过一组实验验证了我们的方法,该实验预测了NAS并行基准和CGPOP并行应用的性能。实验结果表明,所提出的框架可以准确地预测并行程序的执行时间,这些程序的平均误差率为10.86%。

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