Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications

摘要

This research is our first step on the purpose of developing low-complex Viterbi decoder for IoT applications. We evaluate how the values of Viterbi decoder's parameters such as trace back length (L), input data bit-width (D), and LLR truncated value (E), affects to BER and PER of a communication system. The IEEE 802.11a simulator is used because it is considered to be suitable for IoT applications. Our simulation results show that both BER and PER performance are improved if L value increased. However, if L is large enough, i.e., L > 60, the performance improvement becomes insignificant. In addition, both BER and PER performance are continuously improved if D value increases from 1 to 5 bits. The best improvement of both BER performance (i.e., 1.8dB) and PER performance (i.e., 1.5dB) can be seen when D increases from 2 to 3 bits. Thus D = 3 is proposed for Viterbi decoder's hardware development. Surprisingly, when D > 5 both BER and PER performance are degraded if D increases. Finally, our research shows that truncating the LLR value to E = 1.75 helps the Viterbi decoder achieves the best BER and PER performance in case D = 3 bits. Base on these research results, we come to the conclude of using 20 ≤ L ≤ 40, D = 3 bits, and E ≈ 1.75 for future development of low complex Viterbi decoder circuit for IoT applications. Furthermore, in this paper we introduce some mathematics equations for simplifying the Viterbi decoder process.