Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning

摘要

Post-Silicon Tuning is an emerging technology for improving performance-yield of VLSIs under process variations. This paper focuses especially on the post-silicon timing-skew tuning (PSST) via programmable delay elements (PDEs), and proposes a novel tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of costly delay-time measurements. Regarding reliable operation against run-time delay/timing variation, we have introduced the concept of "timing margin in control-value" into PSST, and show how to manage the timing test for PDE tuning considering this kind of timing margin. Proposed PDE tuning algorithm repeats the update of control-value constraint graph (CCG) from the results of setup and hold timing tests, the update of desired PDE setting, and timing test considering timing margin. During the timing test, we need to configure PDEs with test setting patterns which are different from the desired PDE setting. The problem of minimizing the number of test setting patterns is also addressed as a novel problem which arises from timing test considering timing margin.