A hardware/software partitioning algorithm for micro processors based on response time of hardware IPs

摘要

This paper proposes a hardware/software partitioning algorithm based on response time of hardware IPs. We have been developing a new design approach which first determines the hardware IPs, then co-synthesizes a processor core. Our approach realizes an application-specific system LSI including the processor core that contains only the necessary functionalities. We can reduce an unnecessary functionalities by hardware/software partitioning for micro processors based on response time of hardware IPs. Our algorithm obtains hardware response time of hardware IPs at instruction level. That realizes the efficient parallel execution of hardware and software. The experimental results show effectiveness of the proposed algorithm and our new design approach.