Residue arithmetic circuits for RSA encryption

摘要

A fast serial residue multiplier based on signed-digit (SD) number arithmetic circuits is proposed for RSA public-key encryption. A modulo m addition is performed by using two p-digit SD adders and a modulo m multiplier is constructed with one modulo m SD adder, a partial product generator and registers. We present a Booth recoding method to reduce the partial products. When a radix-four Booth code is used, the partial products are reduced to half. The circuit design and simulation results by VHDL show that a high speed RSA public-key encryption processor can be implemented by applying the presented residue multiplier.